Jiangnan Li

I am currently pursuing a Ph.D. in the School of Microelectronics at Fudan University in Shanghai, China, under the supervision of Prof. Lingli Wang. I received my B.S. in Electronic Science and Technology from Northwestern University in 2022. My research interests include:

  • AI Compiler
  • High-Level Synthesis
  • Reconfigurable Computing
  • Hardware/Software Co-Design

Education & Experience

  • 2022.09 - Present: Ph.D. Candidate, School of Microelectronics, Fudan University, Shanghai, China
  • 2026.03 - Present: Intern, Tencent (Qingyun Project), focusing on AI Compiler, Shanghai, China

Selected Publications

  • DataFlowGen: An MLIR-based Compiler for Efficient Dataflow Accelerator Generation. Jiangnan Li, Kaixiang Zhu, Zhengyi Zhang and Lingli Wang. The Chips to Systems Conference (DAC), July 2026

  • DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution. Jiangnan Li, Xianfeng Cao, Kaixiang Zhu, Wenbo Yin, Lingli Wang. 2025 International Conference on Computer-Aided Design (ICCAD), Munich, Germany, October 2025

  • A Collaborative Framework for Multi-Level Multi-Objective Design Space Exploration . Jiangnan Li=, Kaixiang Zhu=, Yuping Bai, Yunfei Dai, Qing He, Yu He, Lingli Wang. Design, Automation and Test in Europe Conference (DATE), April 2026

  • GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping. Jiangnan Li, Chang Cai, Yaya Zhao, Yazhou Yan, Wenbo Yin, Lingli Wang. 2023 International Conference on Field Programmable Technology (ICFPT), Yokohama, Japan, December 2023

  • An MLIR-based Compiler for Hardware Acceleration with Recursion Support. Jiangnan Li, Zhengyi Zhang, Xuegong Zhou, Lingli Wang. 2024 International Conference on Field Programmable Technology (ICFPT), Sydney, December 2024

Open-Source Projects

  • DataFlowGen & DynVec , an MLIR-based Framework for Efficient Dataflow Accelerator Generation.
  • COLA, a Collaborative Framework for Multi-Level Multi-Objective Design Space Exploration.
  • CGRA-Framework, an end-to-end agile design framework to improve energy efficiency on CGRAs.
  • CGRA-Mapper, an integrated framework for compilation, exploration, synthesis, and development of spatial accelerators.
  • MLIR-Recursion, an MLIR compilation pipeline that supports recursive applications in High-Level Synthesis (HLS) workflows.

Selected Awards

  • The First Prize, Fudan Micro Cup National College Students Electronic Design Competition (Software and Hardware Track), 2023.
  • The First Prize Scholarship, Fudan University, 2023.
  • National Scholarship, China, 2020.